Silicon Laboratories SI4421 Instrukcja Użytkownika Pobierz pdf (Strona 7)

Si4702/03-C19

Rev. 1.1 7

Figure 2. Reset Timing Parameters for Busmode Select Method 2 (GPIO3 = 1)

Table 5. Reset Timing Characteristics (Busmode Select Method 2)

1,2,3

Parameter Symbol Test Condition Min Typ Max Unit

GPIO1 and GPIO3 Setup to RST

 t

SRST2

GPIO3 = 1 30 — — ns

GPIO1 and GPIO3 Hold from R

ST t

HRST2

30 — — ns

Notes:

When selecting 2-wire Mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is

high) does not occur within 300 ns before the rising edge of RST

2. When selecting 3-wire Mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the

rising edge of RST

3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until

after the 1st start condition.

70%

30%

SRST2

RST

HRST2

GPIO3

70%

30%

GPIO1

70%

30%

1 2 3 4 5 6 7 8 9 10 11 12 ... 45 46

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Silicon Laboratories SI4421 Instrukcja Użytkownika Strona 7