3. Design
These components are for
internal Silabs use only.
:LUHVFRPPRQWR
SLQSDUWV
No
R103 R106R101
No
No
No
No No
No Yes
NoNo
No Yes
PKG_16.11 & PKG_24.15
PKG_16.3 & PKG_24.4
PKG_16.15 & PKG_24.23
PKG_16.7 & PKG_24.11
PKG_24.16
R102
No
No
Yes
Yes
Yes
No Yes X
XNo
No
Yes
SPI 32 kHz
SPI 27 MHz
SPI 4.9252 MHz
Pin11 Pin3 Pin15Pin7
Pin15 Pin23Pin11
R104 R106R101 R102
No Yes
X
X
No
Yes
No
Yes
No
Yes
Pin16
16 pin sys side strapping table
UART 4.9152 MHz
UART 27 MHz
UART 32 kHz Parallel
PKG_24.17
R105
Pin17
X
X
X
X
Parallel
27 Mhz
4.9152 MHz
SPI
SPI
SPI
No Yes
No Yes
No
No
Yes 27 Mhz
Yes X 4.9152 MHz
32.768 kHzNo No
No No UARTNo Yes 32.768 kHzX
No No UARTNo No No
No No UARTNo No Yes
4.9152 MHz
27 Mhz
24 pin system side strapping table
<<%<DUHDOWHUQDWHIRRWSULQWVDQGIUHTXHQFLHV
7KH9DOXHVRI&&YDU\6HH7KH%20
2QO\RQH6\VWHPVLGHSDUWLV
VROGHUHGDWWLPH8RU8
CTSb AOUT_INTb INTb RIb DCDb
CTSb AOUT_INTb FSYNCH(RI) DCDb
SDO_EECLK_RTSb
DCDb
ESC
AOUT_INTb
RXD
RESETb
XTALI
XTALO
RXD
RTSb
RESETb
DCDb
FSYNCH
RTSb
INTb
ESC
RIb
SDI_EESD
AOUT_INTb
CLKOUT_EECSb_AO
CLKOUT_EECSb_AO
TXD
CTSb
TXD
CTSb
FSYNCH
SDO_EECLK_RTSb
SDO_EECLK_RTSb
SDI_EESD
RIb
AOUT_INTb
FSYNCH
INTb
ESC
DCDb
RIb
SDI_EESD
VDA
XTALO
XTALI
XTALO
AOUT_INTb
CTSb
DCDb
FSYNCH
INTb
RIb
VDA
VDB
RXD
TXD
CTSb
XTALI
RESETb
C1A
C2A
C1A
C2A
VDD
VDD
VDD
VDD
R101 10KR101 10K
C41 33pFC41 33pF
R121 NIR121 NI
R18 1.2KR18 1.2K
R111 200R111 200
R120 NIR120 NI
FB5FB5
C51
0.22uF
C51
0.22uF
R104 10KR104 10K
R102 10KR102 10K
C56
0.1uF
C56
0.1uF
R103 10KR103 10K
C52
0.1uF
C52
0.1uF
R105 10KR105 10K
R112 200R112 200
U13
Si24xx-16 pin
U13
Si24xx-16 pin
CLKIN/XTALI
1
XTALO
2
RIb
3
VDD3.3
4
RXD_SPI_MISO
5
TXD_SPI_MOSI
6
CTSb_SPI_SCLK
7
RESET
8
C2A
9
C1A
10
INTb
11
GND
12
VA
13
ESC
14
DCDb
15
RTSb_SPI_CSb
16
J1
SOCKET 8x2
J1
SOCKET 8x2
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
13
13
15
15
12
12
14
14
16
16
C53
0.22uF
C53
0.22uF
C40 33pFC40 33pF
C55
0.1uF
C55
0.1uF
C54
1uF
C54
1uF
Y3
27 MHz
Y3
27 MHz
GND
2
VCC
4
OUT
3
NC
1
C50
0.1uF
C50
0.1uF
R106 10KR106 10K
R110 200R110 200
Y1B
32.768KHz
Y1B
32.768KHz
U12
Si2493
U12
Si2493
CLKIN/XTALI
1
XTALO
2
CLKOUT/EECSb/A0
3
FSYNCH/D6
4
VD3.3
5
GND
6
VDA
7
RTSb/SPI_CSb/D7
8
VDB
19
GND
20
VD 3.3
21
C2A
13
C1A
14
ESC/D3
22
DCDb/D4
23
SDO/EECLK/D5
24
CTS/SPI_SCLK/CSb
11
RXD/SPI_MISO/RDb
9
TXD/SPI_MOSI/WRb
10
RESET
12
RIb/D1
17
SDI/EESD/D2
18
AOUT/INTb
15
INTb/D0
16
Y1
4.9152MHz
Y1
4.9152MHz
Figure 8. i2493/57/34/15/04 Schematic
(172 strony)
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